Browsing by Author "Dimitrakopoulos, Giorgos"
Now showing items 1-11 of 11
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Article
Automatic Generation of Peak-Power Traffic for Networks-on-Chip
Seitanidis, Ioannis; Nicopoulos, Chrysostomos; Dimitrakopoulos, Giorgos (2019)Early estimation of the peak power consumption of a system under development is crucial in assessing the design's thermal profile and reliability, and in benchmarking the chip-level power management features. In this paper, ...
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Conference Object
Dynamic Adjustment of Test-Sequence Duration for Increasing the Functional Coverage
Takakis, Zacharias; Mangiras, Dimitrios; Nicopoulos, Chrysostomos; Dimitrakopoulos, Giorgos (2019)The importance of functional coverage during front-end verification is steadily increasing. Complete coverage statistics, possibly spanning from block- to top-level, are required as a proof of verification quality and ...
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Conference Object
Error-Shielded Register Renaming Sub-system for a Dynamically Scheduled Out-of-Order Core
Gabor, Ron; Sazeides, Yiannakis; Bramnik, Arkady; Andreou, Alexandros; Nicopoulos, Chrysostomos; Patsidis, Karyofyllis; Konstantinou, Dimitris; Dimitrakopoulos, Giorgos (2019)Emerging mission-critical and functional safety applications require high-performance processors that meet strict reliability requirements against random hardware failures. These requirements touch even sub-systems within ...
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Conference Object
Error-Shielded Register Renaming Sub-system for a Dynamically Scheduled Out-of-Order Core
Gabor, Ron; Sazeides, Yiannakis; Bramnik, Arkady; Andreou, Alexandros; Nicopoulos, Chrysostomos; Patsidis, Karyofyllis; Konstantinou, Dimitris; Dimitrakopoulos, Giorgos (2019)Emerging mission-critical and functional safety applications require high-performance processors that meet strict reliability requirements against random hardware failures. These requirements touch even sub-systems within ...
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Article
A low-cost synthesizable RISC-V dual-issue processor core leveraging the compressed Instruction Set Extension
Patsidis, Karyofyllis; Konstantinou, Dimitris; Nicopoulos, Chrysostomos; Dimitrakopoulos, Giorgos (2018)The RISC-V Instruction Set Architecture (ISA) is becoming an increasingly popular ecosystem for both hardware and software development. In this article, we investigate one of RISC-V’s most versatile ISA extensions, which ...
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Conference Object
Low-power dual-edge-triggered synchronous latency-insensitive systems
Konstantinou, Dimitris; Psarras, Anastasios; Dimitrakopoulos, Giorgos; Nicopoulos, Chrysostomos (2018)Latency-insensitive data flow is a design paradigm that tolerates the latency variability of computations and communications and allows for correct-by-construction module integration. In this paper, we aim to reduce the ...
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Article
The Mesochronous Dual-Clock FIFO Buffer
Konstantinou, Dimitrios; Psarras, Anastasios; Nicopoulos, Chrysostomos; Dimitrakopoulos, Giorgos (2020)To increase system composability and facilitate timing closure, fully synchronous clocking is replaced by more relaxed clocking schemes, such as mesochronous clocking. Under this regime, the modules at the two ends of a ...
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Book Chapter
Monitor and Knob Techniques in Network-on-Chip Architectures
Zoni, Davide; Englezakis, Panayiotis; Chrysanthou, Kypros; Canidio, Andrea; Prodromou, Andreas; Panteli, Andreas; Nicopoulos, Chrysostomos; Dimitrakopoulos, Giorgos; Sazeides, Yiannakis; Fornaciari, William (Springer International Publishing, 2019)This chapter proposes and analyzes two autonomous, hardware-based monitor/knob solutions for Network-on-Chip (NoC) architectures, which operate at the micro-architectural level. The two proposed techniques tackle power and ...
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Book Chapter
Monitor and Knob Techniques in Network-on-Chip Architectures
Zoni, Davide; Englezakis, Panayiotis; Chrysanthou, Kypros; Canidio, Andrea; Prodromou, Andreas; Panteli, Andreas; Nicopoulos, Chrysostomos; Dimitrakopoulos, Giorgos; Sazeides, Yiannakis; Fornaciari, William (Springer International Publishing, 2019)This chapter proposes and analyzes two autonomous, hardware-based monitor/knob solutions for Network-on-Chip (NoC) architectures, which operate at the micro-architectural level. The two proposed techniques tackle power and ...
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Conference Object
Multi-Armed Bandits for Autonomous Timing-driven Design Optimization
Stefanidis, Apostolos; Mangiras, Dimitrios; Nicopoulos, Chrysostomos; Dimitrakopoulos, Giorgos (2019)Timing closure is a complex process that involves many iterative optimization steps applied in various phases of the physical design flow. Cell sizing and transistor threshold selection, as well as datapath and clock ...
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Article
Timing-Driven Placement Optimization Facilitated by Timing-Compatibility Flip-Flop Clustering
Mangiras, Dimitrios; Stefanidis, Apostolos; Seitanidis, Ioannis; Nicopoulos, Chrysostomos; Dimitrakopoulos, Giorgos (2019)Timing-driven placement optimization is applied incrementally in various parts of the flow, together with other timing optimization techniques, to achieve timing closure. In this work, we present a generalized approach for ...